3.2.5.3.5 Multi-Port DDR and SDRAM Controllers
The product embeds a multi-port DDR Controller. This allows to use three additional ports on the MPDDRC to lessen the EBI load from a part of SDRAM accesses. This increases the bandwidth when DDR3(L)/DDR2 and NAND Flash devices are used.
It is controlled by the DDR_MP_EN bit in EBI Chip Select Assignment Register.
When:
- a NAND Flash memory is connected to NANDDAT[7:0] and
- a DDR2-SDRAM is connected to D[15:0],
the bits SFR_CCFG_EBICSA.DDR_MP_EN and SFR_CCFG_EBICSA.NFD0_ON_D16 must both be set before performing the SDRAM initialization.