47.2.1 Power Supply Connections

The following figures show the recommended power supply connections for switched/linear mode, linear mode only and with battery backup.

Figure 47-1. Power Supply Connection for Switching/Linear Mode
Figure 47-2. Power Supply Connection for Linear Mode Only
Figure 47-3. Power Supply Connection for Battery Backup
Table 47-1. Power Supply Connections, VDDCORE or VDDOUT From Internal Regulator
Signal Name Recommended Pin Connection Description
VDDIO 1.62V to 3.63V

Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)

Decoupling/filtering inductor 10µH(1)(3)

 Digital supply voltage
VDDANA 1.62V to 3.63V

Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)

Ferrite bead(4) prevents the VDD noise interfering with VDDANA

 Analog supply voltage
VVDDOUT Switching regulator mode: 10µH inductor with saturation current above 150mA and DCR<1Ω

Linear regulator mode: Not connected

 On-chip switching mode regulator output
VDDCORE 0.9V to 1.2V typical

Decoupling/filtering capacitors 100nF(1)(2) and 1µF(1)

 Linear regulator mode: Core supply voltage output/ external decoupling pin

Switched regulator mode: Core supply voltage input, must be connected to VDDOUT via inductor
VBAT 1.62V to 3.63V when connected(6) External battery supply input
VLCD LCD Bias Voltage

Analog input/output

When VLCD is generated internally, the output voltage range is 2.5V to 3.5V.

When VLCD is provided externally, the input voltage range is 2.4V to 3.6V.

External VLCD capacitor 1µF(1)(5)

Note: Leave VLCD pin unconnected when the LCD controller is not used.
 Powers the LCD voltage pump
GND Common ground Ground
GNDANA Ground for VDDANA Ground for the analog power domain
  1. These values are only given as a typical example.
  2. Decoupling capacitors should be placed close to the device for each supply pin pair in the signal group, low ESR capacitors should be used for better decoupling.
  3. An inductor should be added between the external power and the VDD for power filtering.
  4. A ferrite bead has better filtering performance compared to standard inductor at high frequencies. A ferrite bead can be added between the main power supply (VDDIO) and VDDANA to prevent digital noise from entering the analog power domain. The bead should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz) to separate the digital and analog power domains. Make sure to select a ferrite bead designed for filtering applications with a low DC resistance to avoid a large voltage drop across the ferrite bead.
  5. The external capacitor 1µF on the VLCD pin is only required if VLCD is generated internally (SLCD.CTRLA.XVLCD=0). When the SLCD controller is not used at all, the VLCD pin can remain unconnected - in this case, no external capacitor required, too.
  6. When the VBAT pin is used for battery supply, PB03 (VBAT) cannot be used as PORT I/O pin or for any other multiplexed peripheral signal. VBAT pin should not be powered before it has been properly configured by software for battery supply. Till its configuration, PB03 will behave as a standard I/O regarding leakage.