3 Design Overview 

The following figure illustrates the top-level block diagram of the reference design. The system captures raw data from a dual-camera sensor module and writes it to the fabric DDR4 memory. The captured data is processed through an image processing pipeline, which includes various IP cores such as:
  • Bayer Conversion
  • RGB to YCbCr Transformation
  • YCbCr to RGB Transformation
  • Edge Detection
  • Image Enhancement

Once processed, the data from both camera modules is blended using an alpha blending IP before being displayed on an HDMI-compliant device. The Microprocessor Sub-System (MSS) executes firmware that configures both camera sensor modules through I2C channels. Additionally, a Video Control GUI enables real-time adjustments to video features such as brightness and contrast. This GUI communicates with the design on the board through a UART interface.

Figure 3-1. Top-Level Block Diagram