3.2 MSS Configuration
(Ask a Question)The following table lists the configuration of MSS clock, peripherals, and memory.
| MSS Block | Description |
|---|---|
| MSS Clocks |
MSS PLL reference clock source: 125 MHz MSS CPU clock frequency: 600 MHz |
| Peripherals | I2C: Used for initializing the camera |
| Fabric Interface Controller (FIC) | FIC3_APB_Master: Accessing camera control registers through APB interface |
| Low Power DDR4 (LPDDR4) memory | Low Power DDR4 memory is unused in this Picture-in-Picture design |
| Memory Partitioning | Since LPDDR4 is unused, memory partitioning is not used in the current design |