3.3 Clocking Structure

The following figure shows the clocking structure of the design. PF_CCC_C0 generates the 50 MHz fabric clocks from the REF_CLK generated by PF_XCVR_REF_CLK. This clock drives the APB3 bus interface and provides the reference clock for the PLL inside the PF_DDR4 Controller. The on-board 148.5 MHz on-board oscillator provides a reference clock to generate clocks used in the design.