66.11 POR Characteristics

The figure below provides a general presentation of Power-On-Reset (POR) characteristics.

Figure 66-9. General Presentation of POR Behavior

When a very slow (versus tRST) supply rising slope is applied on the POR VDD pin, the reset time becomes negligible and the reset signal is released when VDD raises higher than VT+.

When a very fast (versus tRST) supply rising slope is applied on the POR VDD pin, the voltage threshold becomes negligible and the reset signal is released after tRST. It is the smallest possible reset time.

Table 66-40. VDDBU Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising–1.3–1.5V
VT-Threshold Voltage Falling–1.22–1.4V
VhysHysteresis Voltage–50–160mV
tRSTReset Timeout Period–890–5100µs
Table 66-41. VDDCORE Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising–0.927–1.075V
VT-Threshold Voltage Falling–0.848–1.025V
VhysHysteresis Voltage–38–109mV
tRSTReset Timeout Period–150–650µs
Table 66-42. VDDANA Power-On Reset Characteristics
SymbolParameterConditionsMinTypMaxUnit
VT+Threshold Voltage Rising–1.3–1.5V
VT-Threshold Voltage Falling–1.22–1.4V
VhysHysteresis Voltage–50–160mV
tRSTReset Timeout Period–130–650µs