40.14 UDPHS Endpoint Control Register (Isochronous Endpoint)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x1.

The reset value for UDPHS_EPTCTL0 is 0x00000001.

Name: UDPHS_EPTCTLx
Offset: 0x010C + x*0x20 [x=0..15]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 SHRT_PCKT        
Access R 
Reset 0 
Bit 2322212019181716 
      BUSY_BANK   
Access R 
Reset 0 
Bit 15141312111098 
  ERR_FLUSHERR_CRC_NTRERR_FL_ISOTXRDY_TRERTX_COMPLTRXRDY_TXKLERR_OVFLW 
Access RRRRRRR 
Reset 0000000 
Bit 76543210 
 MDATA_RXDATAX_RX  INTDIS_DMA AUTO_VALIDEPT_ENABL 
Access RRRRR 
Reset 00000 

Bit 31 – SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset)

For OUT endpoints: Send an Interrupt when a Short Packet has been received.

For IN endpoints: A Short Packet transmission is ensured upon end of the DMA Transfer, thus signaling an end of isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.

ValueDescription
0

Short Packet Interrupt is masked.

1

Short Packet Interrupt is enabled.

Bit 18 – BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset)

For OUT endpoints: An interrupt is sent when all banks are busy.

For IN endpoints: An interrupt is sent when all banks are free.

ValueDescription
0

BUSY_BANK Interrupt is masked.

1

BUSY_BANK Interrupt is enabled.

Bit 14 – ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

Bank Flush Error Interrupt is masked.

1

Bank Flush Error Interrupt is enabled.

Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

ISO CRC error/number of Transaction Error Interrupt is masked.

1

ISO CRC error/number of Transaction Error Interrupt is enabled.

Bit 12 – ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

Error Flow Interrupt is masked.

1

Error Flow Interrupt is enabled.

Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset)

CAUTION: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear.
ValueDescription
0

TX Packet Ready/Transaction Error Interrupt is masked.

1

TX Packet Ready/Transaction Error Interrupt is enabled.

Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

Transmitted IN Data Complete Interrupt is masked.

1

Transmitted IN Data Complete Interrupt is enabled.

Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

Received OUT Data Interrupt is masked.

1

Received OUT Data Interrupt is enabled.

Bit 8 – ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset)

ValueDescription
0

Overflow Error Interrupt is masked.

1

Overflow Error Interrupt is enabled.

Bit 7 – MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)

ValueDescription
0

No effect.

1

Send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has been received.

Bit 6 – DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)

ValueDescription
0

No effect.

1

Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.

Bit 3 – INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset)

If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed.

If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested).

If the exception raised is not associated to a new system bank packet (ex: ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer.

This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.

Bit 1 – AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset)

Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.

For IN Transfer:

If this bit is set, the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.

The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user needs to send a Zero Length Packet by software.

For OUT Transfer:

If this bit is set, the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.

The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s).

Bit 0 – EPT_ENABL Endpoint Enable (cleared upon USB reset)

ValueDescription
0

The endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.

1

The endpoint is enabled according to the device configuration.