26.6.8 RTC Calendar Alarm Register
In UTC mode, this register view is not relevant, see RTC_CALALR (UTC_MODE).
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields.
| Name: | RTC_CALALR |
| Offset: | 0x14 |
| Reset: | 0x01010000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATEEN | DATE[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MTHEN | MONTH[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 31 – DATEEN Date Alarm Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | The date-matching alarm is disabled. |
| 1 | ENABLED | The date-matching alarm is enabled. |
Bits 29:24 – DATE[5:0] Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
Bit 23 – MTHEN Month Alarm Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | The month-matching alarm is disabled. |
| 1 | ENABLED | The month-matching alarm is enabled. |
Bits 20:16 – MONTH[4:0] Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.