23.4.3.3 User Reset

The user reset is entered when a low level is detected on the NRST pin and RSTC_MR.URSTEN is at 1. The NRST input signal is resynchronized with 32 kHz to ensure proper behavior of the system.

The processor reset and the peripheral reset are asserted.

The user reset is left when NRST rises, after a two-cycle resynchronization time and a two-cycle processor start-up. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a user reset.