23.4.3.4 Software Reset

The RSTC offers several commands used to assert the different reset signals. These commands are performed by writing the Control register (RSTC_CR) with the following bits at 1:

• PROCRST–Writing PROCRST at 1 resets the processor, the watchdog timer and all the embedded peripherals, including the memory system, and, in particular, the remap command.

The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts two 32 kHz cycles.

The internal reset signals are asserted as soon as a write access is performed in RSTC_CR and are de-asserted after the re-synchronization and processor start-up time. This is detected on the Main System Bus Clock (MCK). They are released when the software reset is de-asserted, i.e., synchronously to 32 kHz.

If and only if RSTC_CR.PROCRST is set, the RSTC reports the software status in RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP.

As soon as a software operation is detected, RSTC_SR.SRCMP is set. It is cleared as soon as the software reset is left. No other software reset can be performed while RSTC_SR.SRCMP is set, and writing any value in RSTC_CR has no effect.