8 Appendix 4: References
(Ask a Question)This section lists the documents that provide more information about programming and other IP cores used.
- For more information about PolarFire FPGA programming, see PolarFire FPGA and PolarFire SoC FPGA Programming User Guide .
- For more information about the CoreJTAGDEBUG IP core, see CoreJTAGDebug_HB.pdf. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about the MIV_RV32 IP core, see MIV_RV32 Handbook. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about the CoreUARTapb IP core, see CoreUARTapb_HB.pdf. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about the CoreAPB3 IP core, see CoreAPB3_HB.pdf. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about the CoreGPIO IP core, see CoreGPIO_HB.pdf. This user guide can be downloaded from the Libero SoC Catalog.
- For more information about the PolarFire initialization monitor, see PolarFire Family Power-Up and Resets User Guide .
- For more information about how to build a Mi-V processor subsystem for PolarFire devices, see AN4997: PolarFire FPGA Building a Mi-V Processor Subsystem .
- For more information about the PF_CCC IP core, see PolarFire Family Clocking Resources User Guide .
- For more information about Libero, ModelSim, and Synplify, see Libero SoC Documentation .