3.3 ZVS Soft Switching (Zero-Volt-Switching)

The phase-shifted full-bridge topology also introduces circulating currents at the primary side. This happens when both the switching leg switch node voltages overlap, thereby enforcing nearly 0V at the primary side of the transformer. If the transformer and external leakage inductance is carrying any current, then shorting (0V) the primary side transformer terminals causes the current to be constant and results in circulating currents. This has both advantages and disadvantages; it helps charge/discharge any parasitic capacitance mainly coming from the primary side full bridge Coss. Partially or completely charging/discharging MOSFET Coss results in varying degrees of ZVS.

Zero-Volt-Switching means switching the MOSFET ON and OFF with zero voltage across drain and source (V_DS = 0V). This helps reduce the turn ON and turn OFF switching losses of primary side full bridge. While full ZVS is achieved at a certain power level, partial ZVS also increases operating efficiency. ZVS on the primary side switches is achieved by having enough leakage energy to charge and discharge system parasitic capacitance. This includes transformer parasitic capacitance and SiC MOSFET Coss.

ZVS Condition for Leakage Energy

$\frac{1}{2}\left(L_{lk\_t}\right)\left({I_{lk}}^2\right)>\frac{1}{2}\left(C_{oss}\right)\left({Vin}^2\right)$

Where,

• $L_{lk\_t}$ represents total leakage energy at the primary side. This mainly includes main power transformer primary side leakage inductance and any external shim inductance.

$L_{lk\_t}=L_{shim}+L_{lk}$

• $C_{oss}$ represents total parasitic capacitance which loads the primary side. This mainly comes from Phase-Shifted Full-Bridge MOSFET Coss, transformer parasitic capacitance and any reflected secondary side parasitic capacitance coming from Synchronous Rectifier stage.

ZVS condition for Dead time

$t_{\min }=\frac{1}{4}\left(T_r\right)$

$T_r=\frac{1}{f_{res}},f_{res}=1/\left(2\pi \sqrt[]{\left(L_{lk\_t}\right)\left(C_{oss}\right)}\right)$

$t_{\min }=\left(\frac{\pi }{2}\right)\sqrt[]{\left(L_{lk\_t}\right)\left(C_{oss}\right)}$

Where,

• $t_{\min }$ is minimum dead time needed to achieve energy conversion for leakage inductance to parasitic capacitance.
• $f_{res}$ is the resonant frequency of system parasitic inductance and capacitance. $T_r$ is the resonance time period.
• $T_r/4$ results in peak value of the switch-node voltage swing. The dead time on PSFB may be adjusted to switch ON when drain-source voltage reaches maximum or minimum value.