37.2.15 Sleep Mode Operation

The I3C Target module remains fully operational while the device is in Sleep as long as the clock source selected by the I3CxCLK register remains active in Sleep mode. All interrupts will still set the corresponding interrupt flags in Sleep, but only enabled system-level interrupts will wake the device from Sleep. Refer to the Interrupts and DMA Triggers section for more information.

The I3C Target module will participate in any bus transaction as long as the Controller provides SCL clocks and the I3CxCLK selected clock is active. However, any operation that requires CPU clocks (such as a CCC trying to write to a register) will be delayed until the device wakes up from sleep.