37.4.45 I3CxCLK

Name:	I3CxCLK
Address:	0x0B5,0x0E8

Clock Input Selection


Bit	7	6	5	4	3	2	1	0
					CLK[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CLK[3:0] Clock Input Selection

Table 37-22. I3CxCLK Clock Input Selections
CLK	Clock Source
`1111`	Reserved
`1110`	CLC4_OUT
`1101`	CLC3_OUT
`1100`	CLC2_OUT
`1011`	CLC1_OUT
`1010`	TU16B_OUT
`1001`	TU16A_OUT
`1000`	TMR4_OUT
`0111`	TMR2_OUT
`0110`	TMR0_OUT
`0101`	CLKR
`0100`	EXTOSC
`0011`	MFINTOSC (500 kHz)
`0010`	HFINTOSC
`0001`	F_OSC
`0000`	F_OSC/4

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