37.2.9 In-Band Interrupt (IBI)

The MIPI I3C® Specification allows the I3C devices on the bus to generate an In-Band Interrupt (IBI) for the Active Controller to service using the SDA and SCL lines. This makes it possible for the devices on the bus to generate interrupts without using any external interrupt lines.

Each device on the I3C bus has a priority level encoded into its Controller-assigned Dynamic address, where addresses with lower numeric values have higher priority levels. This is a natural outcome of the I3C Address Arbitration, where address bits with value ‘0’ are prioritized over bits with value ‘1’. This means that when multiple devices request IBI at the same time, devices with lower numeric value addresses (and subsequently higher priority levels) will have their IBI requests processed sooner than devices with higher numeric value addresses.

The Target module on this device can perform IBI requests, which is represented in the BCR1 bit (BCR1 = 1). This is communicated to the Controller during the Dynamic Address Assignment procedure or when the Controller requests for it using the GETBCR (Get Bus Characteristics Register) Direct Common Command Code (CCC).
The following conditions must be met for the Target to perform an IBI request by setting the IBIREQ bit. If these conditions are not met, then setting the IBIREQ bit will not have any effect until the conditions are met.
  • The Target has a Dynamic Address assigned
  • IBI is enabled on the bus by the Controller (IBIEN = 1)

The Target can request for an In-Band Interrupt by setting the IBIREQ bit. Once the IBIREQ bit is set, the Target waits for the Bus Available condition and then issues a Start on the bus by pulling the SDA line low (standard IBI). The Active Controller acknowledges the Start condition by sending clocks on the SCL line(1) marking the beginning of the Arbitrable Address Header, during which the Target transmits its Dynamic Address in Read mode (R/W bit = 1) on the bus.

However, the Target does not always need to wait for the Bus Available condition to occur on the bus. If another device on the bus issues a Start signal before the Bus Available condition occurs, the Target participates in the Address Arbitration by transmitting its Dynamic Address on the bus (passive IBI).

Tip:
  1. If the Controller does not acknowledge the Start condition issued by the Target, the Bus Time-out feature can be used to abort the Hot-Join or In-Band Interrupt request.
  2. It is recommended to check the value of IBIEN bit in the I3CxEC Events Command register before requesting an In-Band Interrupt. The Controller can enable/disable In-Band Interrupt (ENINT/DISINT) globally on the bus by broadcasting the ENEC/DISEC CCC (Enable/Disable Target Events Command), which is reflected in the I3CxEC register. If the IBIREQ bit is set when IBIEN = 0, the Target module will begin the IBI process as soon as the Controller enables In-Band Interrupt and IBIEN bit is set by the hardware.
Important:
  1. When an In-Band Interrupt is requested in Static Address SDR mode (SASDRMD = 1), the Target sends its Static Address on the bus for arbitration if a Dynamic Address has not been assigned. If the Target has a Dynamic Address assigned, then the Dynamic Address will be sent on the bus for arbitration.
  2. It is possible that the Target loses arbitration while requesting an IBI when the Controller attempts to write to the Target at the same time. The Controller drives the bus with the Target’s address with R/W = 0 (write, for private write transaction), whereas the Target drives the bus with its own address with R/W = 1 (read, for IBI request). When this happens, the Target loses the arbitration and proceeds forward with the private write transaction with the Controller as described in Private Transaction.
Remember: The MIPI I3C® Specification allows multiple devices on the bus to request for In-Band Interrupt together. In the event of such an occurrence, all eligible devices can participate in the Address Arbitration and the Active Controller will service the device that wins the arbitration.
Once the Target wins the address arbitration and the Controller ACKs the In-Band Interrupt request, the Target then proceeds with sending the Mandatory Data Byte and the Payload on the bus as described in the section below. Upon successful completion of the Hot-Join request, the IBIREQ bit is cleared and the IBIDONEIF flag is set.
If the In-Band Interrupt request is unsuccessful (Controller NACKs the IBI request or the Target loses arbitration), the Target will continue to attempt an IBI request at the next Bus Available condition (standard IBI) or the next Start condition on the bus (passive IBI). This process continues until the IBI request is successfully completed or until the number of unsuccessful attempts reaches the Arbitration Request Retry Limit as specified in the I3CxRETRY register and the IBIEIF error flag is set. The IBIREQ bit clears when the In-Band Interrupt request is completed, regardless of the outcome.

The IBI process that the Target follows is described in Figure 37-44.

Figure 37-44. IBI Process Flowchart