37.2.14 Interrupts and DMA Triggers
The I3C Target module has five top level system interrupts in the PIRx register, as shown in Table 37-17. Refer to the “VIC – Vectored Interrupt Controller” chapter for more information on how to activate and use these interrupts.
When enabled, each of these system level interrupts can wake up the device if the Interrupt condition happens when the device is in Sleep mode. Refer to the “Wake-up From Sleep” section in the “VIC – Vectored Interrupt Controller” chapter for more information. This is important for the I3CxRIF Reset Interrupt since the MIPI I3C® Specification recommends that the device wake up when it receives a Target Reset Pattern in Sleep mode. Refer to the Target Reset Pattern Received While in Sleep section for more information. The I3CxRIF Reset Interrupt can also be used to perform a Reset of the I3C Target module or the entire device as outlined in Target Reset.
Each of these system level interrupts also act as DMA triggers. The interrupts do not need to be enabled with their associated enable bits to be used as triggers for DMA transfers.
Refer to the “Types of Hardware Triggers” section in the “DMA – Direct Memory Access” chapter for more information on how to use these DMA triggers.
| I3C® System Level Interrupts and DMA Triggers | Description | Section Reference |
|---|---|---|
| General Interrupt (I3CxIF) | An OR of all General Interrupts in the I3C module. This is a read-only interrupt flag. The interrupt is cleared when each of the enabled interrupt flags in the I3CxPIRx registers are cleared. | Table 37-18 |
| Error Interrupt (I3CxEIF) | An OR of all Error Interrupts in the I3C module. This is a read-only interrupt flag. The interrupt is cleared when each of the enabled interrupt flags in the I3CxERRIRx registers are cleared. | Table 37-19 |
| Transmit Interrupt (I3CxTXIF) | I3CxTXB Transmit Buffer is empty and ready be written. This is a read-only interrupt flag representing the status of the TXBE bit. The interrupt flag is cleared when I3CxTXB Transmit Buffer becomes full. | 37.2.4.4 Transmit and Receive Buffers and FIFO |
| Receive Interrupt (I3CxRXIF) | I3CxRXB Receive Buffer is full and is ready to be read from. This is a read-only interrupt flag representing the status of the RXBF bit. The interrupt flag is cleared when I3CxRXB Receive Buffer becomes empty. | 37.2.4.4 Transmit and Receive Buffers and FIFO |
| Reset Interrupt (I3CxRIF) | Target Reset Pattern is detected on the bus. The user must read the I3CxRSTACT Defining Byte Register and proceed accordingly. | 37.2.11 Target Reset |
The system level General I3C Interrupt (I3CxIF) is a logical OR of various general interrupts at the I3C module level available through the I3CxPIR0 and I3CxPIR1 registers and are listed in Table 37-18. Each of these interrupts can be individually enabled through the I3CxPIE0 and I3CxPIE1 registers.
The system level Error I3C Interrupt (I3CxEIF) is a logical OR of various error interrupts at the I3C module level available through the I3CxERRIR0 and I3CxERRIR1 registers and are listed in Table 37-19. Each of these interrupts can be individually enabled through the I3CxERRIE0 and I3CxERRIE1 registers.
Figure 37-64 shows how the module level and system level I3C interrupts are activated and how they interact with each other.
- The interrupt flag in the I3CxPIRx or I3CxERRIRx registers will set when the condition generating the interrupt becomes true regardless of whether that interrupt is enabled in the I3CxPIEx or I3CxERRIEx register or not.
- The interrupt flags in I3CxPIRx and I3CxERRIRx once set by the hardware do not self-clear. They must be cleared by the user to re-arm the interrupt.
- To trigger a DMA, the appropriate general or error interrupt must be enabled in the I3CxPIEx or I3CxERRIEx register. This is because only the top system level General and Error Interrupts (I3CxIF and I3CxEIF) can act as DMA triggers. Unless the interrupt is enabled at the module level, the system level flag does not get activated. Refer to Figure 37-64 for more information.
| I3C® Module Level General Interrupts I3CxPIRx | Description | Section Reference |
|---|---|---|
| Start Condition (SCIF) | Start condition detected on the bus in SDR mode (does not apply when the bus is in HDR mode). | 37.2.4.1 Start, Stop and Restart Conditions |
| Stop Condition (PCIF) | Stop condition detected on the bus in SDR mode (does not apply when the bus is in HDR mode). | 37.2.4.1 Start, Stop and Restart Conditions |
| Restart Condition (RSCIF) | Restart condition detected on the bus in SDR mode (does not apply when the bus is in HDR mode). | 37.2.4.1 Start, Stop and Restart Conditions |
| I2C ACK Received (I2CACKIF) | Controller responded with an ACK during an I2C Read Transaction. | 37.2.5 Legacy I2C Transaction on I3C Bus |
| Static Address Match (SADRIF) | Controller transmitted Target’s Static Address on the bus during a Legacy I2C Transaction or in Static Address SDR Mode. | |
| Dynamic Address Match (DADRIF) | Controller transmitted Target’s Dynamic Address on the bus during a Private or Direct CCC Transaction. | |
| Byte Transfer Finished (BTFIF) | Target has completed sending or receiving a data byte during a Private I3C/I2C or an IBI Transaction. | |
| Supported CCC Received (SCCCIF) | Controller has transmitted a CCC that is supported by the Target. This bit is set for all supported Broadcast CCCs and only those supported Direct CCCs that address the Target. | 37.2.7.2 Supported CCCs |
| Transaction Complete (TCOMPIF) | Target has detected a Stop or Restart condition after a Private I3C/I2C or an IBI Transaction. | |
| Dynamic Address Changed (DACHIF) | Controller has altered the Target's Dynamic Address in the I3CxDADR register. This bit is set when a new Dynamic Address is assigned (as a result of Hot-Join request or just regular ENTDAA CCC), changed (using SETNEWDA CCC), or cleared (using RSTDAA CCC). | |
| In-Band Interrupt Done (IBIDONEIF) | In-Band Interrupt request process has completed. The Target was able to send the entire Mandatory Data Byte (I3CxIBIMDB) and Payload to the Controller. This bit also sets when the Controller aborts the IBI transaction. | 37.2.9 In-Band Interrupt (IBI) |
| I3C® Module Level Error Interrupts I3CxERRIRx | Description | Section Reference |
|---|---|---|
| I2C NACK Received (I2CNACKIF) | Controller responded with a NACK during an I2C Read Transaction. | 37.2.5 Legacy I2C Transaction on I3C Bus |
| Transmit Underrun (TXUIF) | Controller attempted to read from an empty Transmit FIFO during Private/I2C Read request. | 37.2.4.4 Transmit and Receive Buffers and FIFO |
| Receive Overrun (RXOIF) | Controller attempted to write to a full Receive FIFO during Private/I2C Write transaction. | 37.2.4.4 Transmit and Receive Buffers and FIFO |
| Hot-Join Error (HJEIF) | Hot-Join request exceeded the arbitration retry limit set in I3CxRETRY register. | 37.2.8 Hot-Join Mechanism |
| In-Band Interrupt Error (IBIEIF) | In-Band Interrupt request exceeded the arbitration retry limit set in I3CxRETRY register. | 37.2.9 In-Band Interrupt (IBI) |
| Bus Error (BUSEIF) | Target detected an TE0-TE6 type error on the bus. This bit is set and can be cleared independently of the I3CxBSTAT register bits. | 37.2.13 Error Detection and Recovery in SDR Mode |
| Bus Time-out (BTOIF) | A Bus Time-out is detected on the bus if the feature is enabled using BTOEN bit. | 37.2.3.4.4 Bus Time-out |
| Unsupported CCC Received (UCCCIF) | Controller has transmitted a CCC that is not supported by the Target. This bit is set for all unsupported Broadcast CCCs and only those unsupported Direct CCCs that address the Target. | 37.2.7.2 Supported CCCs |
| Abort Error (ABEIF) | Controller aborted transmission of IBI Payload or a Private Read data byte by pulling End-of-Data T-bit low (Restart condition). | |
| Maximum Write Length Over Size (MWLOEIF) | Controller attempted to write one more byte than the Maximum Write Length size in I3CxMWL register during Private Write transaction. | 37.2.10.1 Private Write Transaction |
| Transmit Buffer Write Error (TXWEIF) | User attempted to write to I3CxTXB Transmit Buffer when not empty
(TXBE = 0). |
37.2.4.4 Transmit and Receive Buffers and FIFO |
| Receive Buffer Read Error (RXREIF) | User attempted to read from I3CxRXB Receive Buffer when not full
(RXBF = 0). |
37.2.4.4 Transmit and Receive Buffers and FIFO |