37.2.10 Private Transaction

Once the Dynamic Address is assigned and the Target is operating in I3C SDR Mode (OPMD = 0b01), the Controller can communicate to the Target directly by specifying the Target’s Dynamic Address. The Controller uses a Private Write Transfer to write data to the Target directly and a Private Read Transfer to read data from the Target directly.
To address the Target directly, the Controller sends a Start or a Restart(1), followed by the 9-bit I3C Address Header. The address header consists of the Target’s Dynamic Address, followed by a R/W bit and an ACK/NACK bit. The R/W bit is ‘0’ (write) for Private Write Transfer and ‘1’ (read) for Private Read Transfer. The RNW status bits are set according to the R/W bit in the address header if the Target ACKs the request.(2)
If the Dynamic Address in the address header matches with the Target’s Dynamic Address in the I3CxDADR register, the Dynamic Address Match DADRIF flag is set. The ACK/NACK response from the Target depends upon the type of the transaction and the internal settings, as described in the following sections.
When a Private Transaction is initiated, the ACK/NACK response from the Target is controlled by the ACKP bit. When the ACKP bit is cleared (ACKP = 0), the Target normally ACKs a Private Write/Read request, and when the ACKP bit is set (ACKP = 1), the Target always NACKs a Private Write/Read request. For a Private Write request, this ACK/NACK response is strictly based on the ACKP bit setting and is completely independent of the status of the Receive Buffer/FIFO. However, for a Private Read request, in addition to the ACKP bit, the ACK/NACK response from the Target is also controlled by the hardware based on the status of the Transmit Buffer/FIFO. A Private Read request when the Transmit FIFO is empty (TXFNE = 0) will always result in a NACK by the Target and the Transmit Underrun TXUIF error flag is set. A Private Read request is ACK’d by the Target only when there is data available in the Transmit FIFO (TXFNE = 1) and ACKP is cleared. Refer to Table 37-6 for more information.
As a special feature, a one-shot ACK of a Private Write/Read request can be performed by setting the ACKPOS bit. This feature is intended to be used in conjunction with ACKP = 1 setting. When ACKP = 1, the Target always NACKs a Private Write/Read request. In this mode, setting the ACKPOS bit will override the auto-NACK setting and ACK the Private Write/Read request just one time, after which the ACKPOS bit is auto-cleared by the hardware.
Tip: The user can set ACKP = 1 to force a NACK on the bus for Private/I2C Write/Read requests if the firmware is not ready to receive/send the data from/to the Controller. When the firmware is ready, the user can set ACKPOS = 1 to receive/send the next stream of data from/to the Controller. Since the ACKPOS bit is cleared immediately after a one-time ACK, this mode is helpful when the firmware is speed limited and is unable to receive/send data from/to back-to-back Private Write/Read requests.
Important:
  1. The Controller can choose to begin an I3C SDR Transaction by transmitting Start and 7'h7E/W Broadcast Address followed by a Restart before addressing the Target’s Dynamic Address. This allows the Controller to avoid any unnecessary address arbitration issues following a Restart condition.
  2. The RNW status bits only apply to Private I3C/I2C Transfers. The R/W bit in the address header is not captured during non-Private Transactions (like CCC, IBI, or Hot-Join).
Tip: It is recommended for the user to use DMA to read and write from the I3C Transmit and Receive Buffers to ensure that the CPU can keep up with the higher I3C speeds. Refer to the Interrupts and DMA Triggers section and the “DMA - Direct Memory Access” chapter for more information.