37.2.3.3.1 Clock-to-Data Turnaround Time

Clock-to-Data Turnaround Time (TSCO) is the time duration between reception of an SCL edge by the Target and the start of driving an SDA change as shown in Figure 37-5 below. It is the measurement of the total internal delay from the SCL input to the SDA output in the Target, not including factors such as bus capacitance and path delay which are included in the broader computation. The MIPI I3C® Specification requires a maximum Clock-to-Data turnaround delay of 12 ns. The Target module on this device can meet this specification with both the I3C buffers (Low-Voltage Buffer and Fast Schmitt Trigger Buffer) across the entire I3C operating voltage range.

Refer to the "Electrical Specifications" chapter for exact TSCO measurements. The user can notify the Controller of the TSCO value through the I3CxMRS Maximum Read Speed register.

Figure 37-5. Clock-to-Data Turnaround Time