4.2.4 PIOD Pin Description

Table 4-4. System-On-Module Pin Description: PIOD
Pad No.	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral				Reset State (Signal, Dir, PU, PD, HiZ, ST)
Pad No.	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Func	Signal	Dir	IO Set	Reset State (Signal, Dir, PU, PD, HiZ, ST)
121⁽²⁾	VDDIN_3V3	GPIO_CLK	PD0	I/O	–	–	A	LCDPCK	O	2	PIO, I, PU, ST
							B	FLEXCOM4_IO4	O	1
							C	UTXD3	O	2
							F	A23	O	2
113⁽²⁾	VDDIN_3V3	GPIO	PD1	I/O	–	–	A	LCDDEN	O	2	PIO, I, PU, ST
113⁽²⁾	VDDIN_3V3	GPIO	PD1	I/O	–	–	F	A24	O	2	PIO, I, PU, ST
23^{(2), (3)}	VDDIN_3V3	GPIO_CLK	PD2	I/O	–	–	A	URXD1	I	1	PIO, I, PU, ST
23^{(2), (3)}	VDDIN_3V3	GPIO_CLK	PD2	I/O	–	–	F	A25	O	2	PIO, I, PU, ST
24^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD3	I/O	PTCROW0	–	A	UTXD1	O	1	PIO, I, PU, ST
							B	FIQ	I	2
							F	NWAIT	I	2
27^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD4	I/O	PTCROW1	–	A	TWD1	I/O	2	PIO, I, PU, ST
							B	URXD2	I	1
							F	NCS0	O	2
21^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD5	I/O	PTCROW2	–	A	TWCK1	I/O	2	PIO, I, PU, ST
							B	UTXD2	O	1
							F	NCS1	O	2
22^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD6	I/O	PTCROW3	–	B	PCK1	O	1	PIO, I, PU, ST
22^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD6	I/O	PTCROW3	–	F	NCS2	O	2	PIO, I, PU, ST
25^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD7	I/O	PTCROW4	–	F	NWR1/NBS1	O	2	PIO, I, PU, ST
28^{(2), (3)}	VDDIN_3V3	GPIO_AD	PD8	I/O	PTCROW5	–	F	NANDRDY	I	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD9	I/O	–	–	D	GTXCK	O	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD10	I/O	–	–	D	GTXEN	O	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD11	I/O	–	–	D	GRXDV	I	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD12	I/O	–	–	D	GRXER	I	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD13	I/O	–	–	D	GRX0	I	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD14	I/O	–	–	D	GRX1	I	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD15	I/O	–	–	D	GTX0	O	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD16	I/O	–	–	D	GTX1	O	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD17	I/O	–	–	D	GMDC	O	2	PIO, I, PU, ST
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD18	I/O	–	–	D	GMDIO	I/O	2	PIO, I, PU, ST
58⁽³⁾	VDDIN_3V3	GPIO_AD	PD19	I/O	AD0	–	A	PCK0	O	1	PIO, I, PU, ST
							B	TWD1	I/O	3
							C	URXD2	I	3
57⁽³⁾	VDDIN_3V3	GPIO_AD	PD20	I/O	AD1	–	A	TIOA2	I/O	3	PIO, I, PU, ST
							B	TWCK1	I/O	3
							C	UTXD2	O	3
19^{(1, 4)}	VDDIN_3V3	GPIO_AD	PD21	I/O	–	–	B	TWD0	I/O	4	PIO, I, PU, ST
20^{(1, 4)}	VDDIN_3V3	GPIO_AD	PD22	I/O	–	–	B	TWCK0	I/O	4	PIO, I, PU, ST
30⁽³⁾	VDDIN_3V3	GPIO_AD	PD23	I/O	AD4	–	A	URXD2	I	2	PIO, I, PU, ST
29⁽³⁾	VDDIN_3V3	GPIO_AD	PD24	I/O	AD5	–	A	UTXD2	O	2	PIO, I, PU, ST
110	VDDIN_3V3	GPIO_AD	PD25	I/O	AD6	–	A	SPI1_SPCK	O	3	PIO, I, PU, ST
34	VDDIN_3V3	GPIO_AD	PD26	I/O	AD7	–	A	SPI1_MOSI	I/O	3	PIO, I, PU, ST
34	VDDIN_3V3	GPIO_AD	PD26	I/O	AD7	–	C	FLEXCOM2_IO0	I/O	2	PIO, I, PU, ST
53	VDDIN_3V3	GPIO_AD	PD27	I/O	AD8	–	A	SPI1_MISO	I/O	3	PIO, I, PU, ST
							B	TCK	I	3
							C	FLEXCOM2_IO1	I/O	2
51	VDDIN_3V3	GPIO_AD	PD28	I/O	AD9	–	A	SPI1_NPCS0	I/O	3	PIO, I, PU, ST
							B	TDI	I	3
							C	FLEXCOM2_IO2	I/O	2
52⁽²⁾	VDDIN_3V3	GPIO_AD	PD29	I/O	AD10	–	A	SPI1_NPCS1	O	3	PIO, I, PU, ST
							B	TDO	O	3
							C	FLEXCOM2_IO3	O	2
							D	TIOA3	I/O	3
54⁽²⁾	VDDIN_3V3	GPIO_AD	PD30	I/O	AD11	–	A	SPI1_NPCS2	O	3	PIO, I, PU, ST
							B	TMS	I	3
							C	FLEXCOM2_IO4	O	2
							D	TIOB3	I/O	3
N/A⁽¹⁾	VDDIN_3V3	GPIO_AD	PD31	I/O	–	–	C	IRQ	I	4	PIO, I, PU, ST

Note:

Fixed feature due to the SOM internal connection.
Limited feature compared to SAMA5D2 due to the SOM internal use of specific functionality, for example, QSPI, GMAC.
Limited feature compared to SAMA5D2 due to the use of a part of the functionality for other features in the SOM, for example, GMAC, ISC, Flexcom, etc.
Signal is internally pulled up with a 2.2 kΩ resistor.