4.2.5 System Pin Description

Table 4-5. System-On-Module Pin Description: System
Pin Number	PIO	Power Rail	Designation	Type
61	CLK_AUDIO	VDDIN_3V3	Audio clock	Output
64	COMPN	VDDBU	External analog comparator input	Input
63	COMPP	VDDBU	External analog comparator input	Input
126	DIS_BOOT⁽¹⁾	VDDIN_3V3	QSPI Interface Disable pin	Input
67	USBA_M	VDDIN_3V3	USB Device High-speed Data -	–
68	USBA_P	VDDIN_3V3	USB Device High-speed Data +	–
70	USBB_M	VDDIN_3V3	USB Host Port B High-speed Data -	–
71	USBB_P	VDDIN_3V3	USB Host Port B High-speed Data +	–
74	DATA	VDDHSIC	USB High-speed Inter-Chip Data	–
73	STROBE	VDDHSIC	USB High-speed Inter-Chip Strobe	–
60	NRST⁽¹⁾	VDDIN_3V3	Microprocessor reset	Input / Active Low
33	PIOBU1	VDDBU	Tamper or Wake-up input	Input
44	PIOBU2	VDDBU	Tamper or Wake-up input	Input
48	PIOBU3	VDDBU	Tamper or Wake-up input	Input
47	PIOBU4	VDDBU	Tamper or Wake-up input	Input
46	PIOBU5	VDDBU	Tamper or Wake-up input	Input
59	PIOBU6	VDDBU	Tamper or Wake-up input	Input
45	PIOBU7	VDDBU	Tamper or Wake-up input	Input
32	RXD	VDDBU	Low-Power Asynchronous Receiver	Input
35	SHDN⁽²⁾	VDDBU	Shutdown Control	Output
49	WKUP	VDDBU	Wake-up	Input
36	ETH_LED0⁽¹⁾	VDDIN_3V3	Status LED control for Ethernet ports	Output
37	ETH_RXM	± 2.5V	Physical receive or transmit signal (– differential)	I/O
38	ETH_RXP	± 2.5V	Physical receive or transmit signal (+ differential)	I/O
40	ETH_TXM	± 2.5V	Physical receive or transmit signal (– differential)	I/O
41	ETH_TXP	± 2.5V	Physical receive or transmit signal (+ differential)	I/O

Note: