32.4.12 SPI Mode Requirements

Table 32-18. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
SP70*

TSSL2SCH,

TSSL2SCL

SS↓ to SCK↓ or SCK↑ input2.25*TCY——ns
SP71*TSCHSCK input high time (Slave mode)TCY + 20——ns
SP72*TSCLSCK input low time (Slave mode)TCY + 20——ns
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge100——ns
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge100——ns
SP75*TDORSDO data output rise time—2550ns1.8V ≤ VDD ≤ 5.5V
SP76*TDOFSDO data output fall time—1025ns
SP77*TSSH2DOZSS↑ to SDO output high-impedance10—50ns
SP78*TSCRSCK output rise time (Master mode)—2550ns1.8V ≤ VDD ≤ 5.5V
SP79*TSCFSCK output fall time (Master mode)—1025ns
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge——145ns1.8V ≤ VDD ≤ 5.5V
SP81*

TDOV2SCH,

TDOV2SCL

SDO data output setup to SCK edge1 TCY——ns
SP82*TSSL2DOVSDO data output valid after SS↓ edge——50ns
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑after SCK edge1.5 TCY + 40——ns

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Figure 32-15. SPI Master Mode Timing (CKE = 0, SMP = 0)
Note: Refer to Figure 32-3 for load conditions.
Figure 32-16. SPI Master Mode Timing (CKE = 1, SMP = 1)
Note: Refer to Figure 32-3 for load conditions.
Figure 32-17. SPI Slave Mode Timing (CKE = 0)
Note: Refer to Figure 32-3 for load conditions.
Figure 32-18. SPI Slave Mode Timing (CKE = 1)
Note: Refer to Figure 32-3 for load conditions.