11.4 Register Summary: NVM Control
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0F7D | Reserved | |||||||||
0x0F7E | NVMADR | 7:0 | NVMADRL[7:0] | |||||||
15:8 | NVMADRH[1:0] | |||||||||
0x0F80 | NVMDAT | 7:0 | NVMDAT[7:0] | |||||||
0x0F81 | NVMCON1 | 7:0 | NVMREG[1:0] | FREE | WRERR | WREN | WR | RD | ||
0x0F82 | NVMCON2 | 7:0 | NVMCON2[7:0] | |||||||
0x0F83 ... 0x0FF4 | Reserved | |||||||||
0x0FF5 | TABLAT | 7:0 | TABLAT[7:0] | |||||||
0x0FF6 | TBLPTR | 7:0 | TBLPTRL[7:0] | |||||||
15:8 | TBLPTRH[7:0] | |||||||||
23:16 | TBLPTR21 | TBLPTRU[4:0] |