12.2.2 Writing Access

The WREN bit must be set to enable writes. This prevents accidental writes to the CONFIG words due to errant (unexpected) code execution. The WREN bit must be kept clear at all times, except when updating the CONFIG words. The WREN bit is not cleared by hardware. The WR bit will be inhibited from being set unless the WREN bit is set.

The user needs to load the TBLPTR and TABLAT register with the respective address and data before executing the write command. An unlock sequence needs to be followed to enable the write (see NVM Unlock Sequence). When attepmting to write the Configuration words, if the WRTC configuration bit is zero or if TBLPTR points an invalid address location (see Table 12-1), then the WR bit is cleared without any effect and the WRERR bit is set.

A single CONFIG word byte is written immediately and the operation includes an implicit erase cycle for that byte (it is not necessary to set FREE). CPU execution is stalled and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag (NVMIF) bit is set. The new CONFIG value takes effect when the CPU resumes operation.