12.5.1 NVMCON1

Nonvolatile Memory Control 1 Register

Note:

This can only be used with PFM.
This bit is set when WR = 1 and clears when the internal programming timer expires or the write is completed successfully.
Bit must be cleared by the user; hardware will not clear this bit.
Bit may be written to ‘1’ by the user to implement test sequences.
This bit can only be set by following the sequence described in NVM Unlock Sequence.
Operations are self-timed and the WR bit is cleared by hardware when complete.
Once a write operation is initiated, setting this bit to zero will have no effect.
The bit can only be set in software. The bit is cleared by hardware when the operation is complete.

Name:	NVMCON1
Offset:	0xF81


Bit	7	6	5	4	3	2	1	0
	NVMREG[1:0]			FREE	WRERR	WREN	WR	RD
Access	R/W	R/W		R/S/HC	R/W/HS	R/W	R/S/HC	R/S/HC
Reset	0	0		0		0	0	0

Bits 7:6 – NVMREG[1:0] NVM Region Selection bits

Value	Description
10	PFM locations write access
x1	User IDs, Configuration Bits, Rev ID and Device ID locations write access
00	Data EEPROM Memory locations write access

Bit 4 – FREE

Program Flash Memory Erase Enable bit⁽¹⁾

Value	Description
1	Performs an erase operation on the next WR command
0	The next WR command performs a write operation

Bit 3 – WRERR

Write-Reset Error Flag bit^(2,3,4)

Value	Description
1	A write operation was interrupted by a Reset (hardware set), or the WR bit was set during one of the following conditions: an invalid address is accessed NVMREG and address do not point to the same region  a write-protected address is accessed.
0	All write operations have completed normally

Bit 2 – WREN Program/Erase Enable bit

Value	Description
1	Allows program/erase and refresh cycles
0	Inhibits programming/erasing and user refresh of NVM

Bit 1 – WR

Write Control bit^(5,6,7)

Value	Name	Description
1	NVMREG = 00	Initiates an erase/program cycle at the corresponding Data EEPROM Memory location specified by NVMADR
1	NVMREG = 10 and TBLPTR21 = 0	Initiates the PFM write operation with data from the holding registers
1	NVMREG = x1 and TBLPTR21 = 1	Initiates the User ID write operation with data from the holding registers or single Config byte at TBLPTR
0	NVMREG = xx	NVM program/erase operation is complete and inactive

Bit 0 – RD

Read Control bit⁽⁸⁾

Value	Description
1	Initiates a read at address pointed by NVMREG and NVMADR, and loads data into NVMDAT
0	NVM read operation is complete and inactive

This can only be used with PFM. This bit is set when WR = 1 and clears when the internal programming timer expires or the write is completed successfully. Bit must be cleared by the user; hardware will not clear this bit. Bit may be written to ‘1’ by the user to implement test sequences. This bit can only be set by following the sequence described in NVM Unlock Sequence. Operations are self-timed and the WR bit is cleared by hardware when complete. Once a write operation is initiated, setting this bit to zero will have no effect. The bit can only be set in software. The bit is cleared by hardware when the operation is complete.