21.1 Timer2 Operation

Timer2 operates in three major modes:

• Free Running Period
• One Shot
• Monostable

Within each mode there are several options for starting, stopping, and reset. Table 21-1 lists the options.

In all modes, the T2TMR count register is incremented on the rising edge of the clock signal from the programmable prescaler. When T2TMR equals T2PR, a high level is output to the postscaler counter. T2TMR is cleared on the next clock input.

An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset. In Gate modes, the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes, the T2TMR count is reset on either the level or edge from the external source.

The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events:

• A write to the T2TMR register
• A write to the T2CON register
• Any device Reset
• External Reset Source event that resets the timer
  Important: T2TMR is not cleared when T2CON is written.