21.5 Operating Modes

The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode.

Table 21-1. Operating Modes Table
ModeMODE[4:0]Output OperationOperationTimer Control
[4:3][2:0]StartResetStop
Free-

Running Period

00000Period PulseSoftware gate (Figure 21-3)ON = 1—ON = 0
001Hardware gate, active-high

(Figure 21-4)

ON = 1 and

TMRx_ers = 1

—ON = 0 or

TMRx_ers = 0

010Hardware gate, active-lowON = 1 and

TMRx_ers = 0

—ON = 0 or

TMRx_ers = 1

011Period Pulse

with

Hardware Reset

Rising or falling edge ResetON = 1TMRx_ers ↕ON = 0
100Rising edge Reset (Figure 21-5)TMRx_ers ↑
101Falling edge ResetTMRx_ers ↓
110Low-level ResetTMRx_ers = 0ON = 0 or

TMRx_ers = 0

111High-level Reset (Figure 21-6)TMRx_ers = 1ON = 0 or

TMRx_ers = 1

One Shot01000One-shotSoftware start (Figure 21-7)ON = 1—ON = 0 or

Next clock after

TMRx = PRx

(Note 2)

001Edge-

Triggered Start

(Note 1)

Rising edge start (Figure 21-8)ON = 1 and

TMRx_ers ↑

—
010Falling edge startON = 1 and

TMRx_ers ↓

—
011Any edge startON = 1 and

TMRx_ers ↕

—
100Edge-

Triggered Start

and

Hardware Reset

(Note 1)

Rising edge start and

Rising edge Reset (Figure 21-9)

ON = 1 and

TMRx_ers ↑

TMRx_ers ↑
101Falling edge start and

Falling edge Reset

ON = 1 and

TMRx_ers ↓

TMRx_ers ↓
110Rising edge start and

Low-level Reset (Figure 21-10)

ON = 1 and

TMRx_ers ↑

TMRx_ers = 0
111Falling edge start and

High-level Reset

ON = 1 and

TMRx_ers ↓

TMRx_ers = 1
Monostable10000Reserved
001Edge-

Triggered Start

(Note 1)

Rising edge start

(Figure 21-11)

ON = 1 and

TMRx_ers ↑

—ON = 0 or

Next clock after

TMRx = PRx

(Note 3)

010Falling edge startON = 1 and

TMRx_ers ↓

—
011Any edge startON = 1 and

TMRx_ers ↕

—
Reserved100Reserved
Reserved101Reserved
One Shot110Level-

Triggered Start

and

Hardware Reset

High-level start and

Low-level Reset (Figure 21-12)

ON = 1 and

TMRx_ers = 1

TMRx_ers = 0ON = 0 or

Held in Reset

(Note 2)

111Low-level start and

High-level Reset

ON = 1 and

TMRx_ers = 0

TMRx_ers = 1
Reserved11xxxReserved
Note:
  1. If ON = 0, then an edge is required to restart the timer after ON = 1.
  2. When T2TMR = T2PR, then the next clock clears ON and stops T2TMR at 0x00.
  3. When T2TMR = T2PR, then the next clock stops T2TMR at 0x00 but does not clear ON.