5.3.1 New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits
The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits select the system clock source and frequency that are used for the CPU and peripherals.
When new values of NOSC and NDIV are written to OSCCON1, the current oscillator
selection will continue to operate while waiting for the new clock source to indicate that
it is stable and ready. In some cases, the newly requested source may already be in use,
and is ready immediately. In the case of a divider-only change, the new and old sources are
the same, so the source will be ready immediately. The device may enter Sleep while waiting
for the switch.
When the new oscillator is ready, the New Oscillator Ready (NOSCR)
bit is set and also the Clock Switch Interrupt Flag (CSWIF) bit of PIR1 sets. If Clock
Switch Interrupts are enabled (CSWIE =
1), an
interrupt will be generated at that time. The Oscillator Ready (ORDY)
bit can also be polled to determine when the oscillator is ready in lieu of an
interrupt.Important: The CSWIF interrupt will not wake the system from Sleep.
If the Clock Switch Hold (CSWHOLD) bit is clear, the oscillator switch will occur when the New Oscillator
is Ready bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at
the new oscillator setting.
If CSWHOLD is set, the oscillator switch is suspended, while execution continues
using the current (old) clock source. When the NOSCR
bit is set, software will:
If DOZE is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during that cycle.
Changing the clock post-divider without changing the clock source
(i.e., changing FOSC from 1 MHz to 2 MHz) is handled in the same manner as a
clock source change, as described previously. The clock source will already be active, so
the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0) for the switch to complete.