5.6.1 OSCCON1

Oscillator Control Register1
Note:
  1. The default value (f/f) is determined by the CONFIG1[RSTOSC] Configuration bits. See Table 5-2.
  2. If NOSC is written with a reserved value (Table 5-3), the operation is ignored and NOSC is not written.
  3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value.
  4. EXTOSC must meet the PLL specifications.
  5. EXTOSC configured by CONFIG1[FEXTOSC].
  6. HFINTOSC frequency is set with the HFFRQ bits.
  7. EXTOSC must meet the PLL specifications.
Name: OSCCON1
Offset: 0xED8

Bit 76543210 
  NOSC[2:0]NDIV[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset fffffff 

Bits 6:4 – NOSC[2:0]  New Oscillator Source Request bits(1,2,3)

The setting requests a source oscillator and PLL combination per Table 5-3.

Table 5-2. Default Oscillator Settings
CONFIG1[RSTOSC]SFR Reset Values (fff ffff)Initial FOSC Frequency
NOSC/COSCNDIV/CDIVOSCFRQ
11111100004 MHzEXTOSC per FEXTOSC
1101100010FOSC = 1 MHz (4 MHz/4)
1011010000LFINTOSC
1001000000SOSC
011Reserved
01001000004 MHzEXTOSC + 4xPLL(4)
001Reserved
000110000064 MHzFOSC = 64 MHz
Table 5-3. NOSC Bit Settings
NOSC[2:0]Clock Source
111EXTOSC(5)
110HFINTOSC(6)
101LFINTOSC
100SOSC
011Reserved
010EXTOSC + 4x PLL(7)
001Reserved
000Reserved

Bits 3:0 – NDIV[3:0]  New Divider Selection Request bits(2,3)

The setting determines the new postscaler division ratio per Table 5-1.

Table 5-1. NDIV Bit Settings
NDIV[3:0]Clock Divider
1111-1010Reserved
1001512
1000256
0111128
011064
010132
010016
00118
00104
00012
00001
The default value (f/f) is determined by the CONFIG1[RSTOSC] Configuration bits. See Table   1.If NOSC is written with a reserved value (Table   2), the operation is ignored and NOSC is not written.When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value.EXTOSC must meet the PLL specifications.EXTOSC configured by CONFIG1[FEXTOSC].HFINTOSC frequency is set with the HFFRQHFINTOSC Frequency Selection bits bits.EXTOSC must meet the PLL specifications.