6.2 Programmable Clock Divider

The module takes the clock input and divides it based on the value of the DIV bits.

The following configurations are available:

• Base F_OSC value
• F_OSC divided by 2
• F_OSC divided by 4
• F_OSC divided by 8
• F_OSC divided by 16
• F_OSC divided by 32
• F_OSC divided by 64
• F_OSC divided by 128

The clock divider values can be changed while the module is enabled. However, to prevent glitches on the output, the DIV bits may be only changed when the module is disabled (EN = 0).