6.6.1 CLKRCON

Reference Clock Control Register
Note:
  1. Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.
Name: CLKRCON
Offset: 0xF3E

Bit 76543210 
 EN  DC[1:0]DIV[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 010000 

Bit 7 – EN

Reference Clock Module Enable bit
ValueDescription
1

Reference clock module enabled
0

Reference clock module is disabled

Bits 4:3 – DC[1:0]

Reference Clock Duty Cycle bits(1)
ValueDescription
11

Clock outputs duty cycle of 75%
10

Clock outputs duty cycle of 50%
01

Clock outputs duty cycle of 25%
00

Clock outputs duty cycle of 0%

Bits 2:0 – DIV[2:0]

Reference Clock Divider bits
ValueDescription
111

Base clock value divided by 128
110

Base clock value divided by 64
101

Base clock value divided by 32
100

Base clock value divided by 16
011

Base clock value divided by 8
010

Base clock value divided by 4
001

Base clock value divided by 2
000

Base clock value
Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.