6.6.1 CLKRCON

Reference Clock Control Register

Note:

Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.

Name:	CLKRCON
Offset:	0xF3E


Bit	7	6	5	4	3	2	1	0
	EN			DC[1:0]		DIV[2:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			1	0	0	0	0

Bit 7 – EN

Reference Clock Module Enable bit

Value	Description
`1`	Reference clock module enabled
`0`	Reference clock module is disabled

Bits 4:3 – DC[1:0]

Reference Clock Duty Cycle bits⁽¹⁾

Value	Description
`11`	Clock outputs duty cycle of 75%
`10`	Clock outputs duty cycle of 50%
`01`	Clock outputs duty cycle of 25%
`00`	Clock outputs duty cycle of 0%

Bits 2:0 – DIV[2:0]

Reference Clock Divider bits

Value	Description
`111`	Base clock value divided by 128
`110`	Base clock value divided by 64
`101`	Base clock value divided by 32
`100`	Base clock value divided by 16
`011`	Base clock value divided by 8
`010`	Base clock value divided by 4
`001`	Base clock value divided by 2
`000`	Base clock value

Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.

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