27.3 Baud Rate Generator

The MSSP module has a Baud Rate Generator (BRG) available for clock generation in both I²C and SPI Host modes. The BRG reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the BRG will automatically begin counting down. MSSP Baud Rate Generator Frequency Equation shows how the value for SSPxADD is calculated.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.

An internal Reload signal, shown in Figure 27-41, triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line.

Table 27-2 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.

MSSP Baud Rate Generator Frequency Equation

F_{C L O C K} = \frac{F_{O S C}}{4 \times (S S P x A D D + 1)}

Figure 27-41. Baud Rate Generator Block Diagram

Important: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I²C. This is an implementation limitation.

Table 27-2. MSSP Clock Rate w/BRG
F_OSC	F_CY	BRG Value	F_CLOCK  (2 Rollovers of BRG)
32 MHz	8 MHz	13h	400 kHz
32 MHz	8 MHz	19h	308 kHz
32 MHz	8 MHz	4Fh	100 kHz
16 MHz	4 MHz	09h	400 kHz
16 MHz	4 MHz	0Ch	308 kHz
16 MHz	4 MHz	27h	100 kHz
4 MHz	1 MHz	09h	100 kHz
Note: Refer to the I/O port electrical specifications in the “Electrical Specifications” chapter, Internal Oscillator Parameters, to ensure the system is designed to support all requirements.