16.13.3 DMAnCON1

DMA Control Register 1
Name: DMAnCON1
Offset: 0x0FD

Bit 76543210 
 DMODE[1:0]DSTPSMR[1:0]SMODE[1:0]SSTP 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:6 – DMODE[1:0] Destination Address Mode Selection

ValueDescription
11Reserved, do not use
10Destination Pointer (DMADPTR) is decremented after each transfer
01Destination Pointer (DMADPTR) is incremented after each transfer
00Destination Pointer (DMADPTR) remains unchanged after each transfer

Bit 5 – DSTP Destination Counter Reload Stop

ValueDescription
1SIRQEN bit is cleared when destination counter reloads
0SIRQEN bit is not cleared when destination counter reloads

Bits 4:3 – SMR[1:0] Source Memory Region Selection

ValueDescription
1xData EEPROM is selected as the DMA source memory
01Program Flash Memory is selected as the DMA source memory
00SFR/GPR data space is selected as the DMA source memory

Bits 2:1 – SMODE[1:0] Source Address Mode Selection

ValueDescription
11Reserved, do not use
10Source Pointer (DMASPTR) is decremented after each transfer
01Source Pointer (DMASPTR) is incremented after each transfer
00Source Pointer (DMASPTR) remains unchanged after each transfer

Bit 0 – SSTP Source Counter Reload Stop

ValueDescription
1SIRQEN bit is cleared when source counter reloads
0SIRQEN bit is not cleared when source counter reloads