35.20.13 UxP3
Note: The individual
bytes in this multibyte register can be accessed with the following register
names:
- UxP3H: Accesses the high byte P3[8]
- UxP3L: Accesses the low byte P3[7:0]
Name: | UxP3 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
P3[8] | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
P3[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 8 – P3[8] Parameter 3 Most Significant bit
Value | Name | Description |
---|---|---|
n | MODE = DMX | Most Significant bit of last address of receive block |
x | All other modes/Limited featured UART | Not used |
Bits 7:0 – P3[7:0] Parameter 3 Least Significant bits
Value | Name | Description |
---|---|---|
n | MODE = DMX | Least Significant bits of last address of receive block |
n | MODE = LIN Client | Number of data bytes to receive |
n | MODE = Asynchronous Address | Receiver address mask. Received address is XOR’d with UxP2L, then AND’d with UxP3L. Match occurs when result is zero. |
x | All other modes | Not used |