35.20.11 UxP1
Note: The individual
bytes in this multibyte register can be accessed with the following register
names:
- UxP1H: Accesses the high byte P1[8]
- UxP1L: Accesses the low byte P1[7:0]
Name: | UxP1 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
P1[8] | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
P1[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 8 – P1[8] Parameter 1 Most Significant bit
Value | Name | Description |
---|---|---|
n | MODE = DMX | Most Significant bit of number of bytes to transmit between Start Code and automatic Break generation |
n | MODE = DALI Control Device | Most Significant bit of Idle time delay after which a Forward Frame is sent. Measured in half-bit periods. |
n | MODE = DALI Control Gear | Most Significant bit of delay between the end of a Forward Frame and the start of the Back Frame. Measured in half-bit periods. |
x | All other modes/Limited featured UART | Not used |
Bits 7:0 – P1[7:0] Parameter 1 Least Significant bits
Value | Name | Description |
---|---|---|
n | MODE = DMX | Least Significant bits of number of bytes to transmit between Start Code and automatic Break generation |
n | MODE = DALI Control Device | Least Significant bits of Idle time delay after which a Forward Frame is sent. Measured in half-bit periods. |
n | MODE = DALI Control Gear | Least Significant bits of delay between the end of a Forward Frame and the start of the Back Frame. Measured in half-bit periods. |
n | MODE = LIN | PID to transmit (Only Least Significant six bits used) |
n | MODE = Asynchronous Address | Address
to transmit (9th transmit bit automatically set to
‘1 ’) |
x | All other modes | Not used |