35.20.2 UxCON1
Note:
- This bit is read-only in LIN, DMX and DALI modes.
| Name: | UxCON1 |
| Offset: | 0x2AC,0x2BF,0x2D2,0x2E5,0x2F8 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ON | WUE | RXBIMD | BRKOVR | SENDB | |||||
| Access | R/W | R/W/HC | R/W | R/W | R/W/HC | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ON Serial Port Enable
| Value | Description |
|---|---|
| 1 | Serial port enabled |
| 0 | Serial port disabled (held in Reset) |
Bit 4 – WUE Wake-Up Enable
| Value | Description |
|---|---|
| 1 | Receiver is waiting for falling RX input edge which will set the UxIF bit. Cleared by hardware on wake-up event. Also requires the UxIE bit of PIEx to enable wake. |
| 0 | Receiver operates normally |
Bit 3 – RXBIMD Receive Break Interrupt Mode Select
| Value | Description |
|---|---|
| 1 | Set RXBKIF immediately when RX in has been low for the minimum Break time |
| 0 | Set RXBKIF on rising RX input after RX in has been low for the minimum Break time |
Bit 1 – BRKOVR Send Break Software Override
| Value | Description |
|---|---|
| 1 | TX output is forced to non-Idle state |
| 0 | TX output is driven by transmit shift register |
Bit 0 – SENDB Send Break Control(1)
| Value | Description |
|---|---|
| 1 | Output Break upon UxTXB write. Written byte follows Break. Bit is cleared by hardware. |
| 0 | Break transmission completed or disabled |