1.4 Demo Design
(Ask a Question)The low-power design is illustrated in the following block diagram.
The PolarFire Fabric block instantiates a counter logic along with 500 µSRAM, 500 LSRAM, and 500 Mathblocks which utilizes 70% of four input LUT and DFF.
In the XCVR_Top SmartDesign, transceiver block is instantiated and looped back internally on the PolarFire Evaluation kit from Lane 2 to Lane 3. The CoreABC and DRI blocks enable the user to dynamically reconfigure the XCVR registers.
The demo design flow is described as follows:
- The DEVICE_INIT_DONE signal of the PF_INIT_MONITOR block is asserted after the device is initialized.
- CoreReset_PF IP core is used to control reset signal of the Fabric_Logic_0 and XCVR_Top blocks.
- The PF_CCC_0 block provides the following fabric clocks:
- CLK: 100 MHz clock for the fabric
- CLK1: 100 MHz clock for the µSRAM blocks
- CLK2: 100 MHz clock for the LSRAM blocks
- CLK3: 100 MHz clock for Mathblocks
- These separate clocks are provided in the design to gate clocks to each fabric block, if required. The transceiver (PF_XCVR) block instantiates the transceiver in 8b/10b mode. This block receives clock from the REF_CLK signal of PF_XCVR_REF_CLK_0. The PF_TX_PLL_0 block also derives its reference clock from REF_CLK of PF_XCVR_REF_CLK_0.
- PLL_Powerdown port is used to enable the PLL Powerdown option.
- Gate_en_in signal is fed to Gate Control block and output of the Gate Control Block is connected to OUT0, 1, and 2_FABCLK_GATED_0_EN.
- OUT3_FABCLK_GATED_0_EN is connected High.
- The TX and RX lanes of the transceiver are looped back using on board PCB loopback.
- The pattern_gen_0 block is implemented to send data to the transceiver block. The pattern_chk_0 block is implemented to check errors in the data received by the transceiver block.
- DRI interface is used to configure the XCVR/TX_PLL in ON and OFF mode.
Two programming job files are provided with this demo.
- With low-power options (
PF_Demo_Low_power.job
). - Without using low-power options
(
PF_Demo_Normal.job
)