3.4.9 Video LVDS Interface
The SAM9X75-Curiosity board embeds a 4-lane LVDS interface to be used with LVDS compatible displays.
The following figure shows the video LVDS interface.
The following table shows the video LVDS interface signal description.
| Pin No. | PIO | Signal Name | Signal Description |
|---|---|---|---|
| 1, 2, 3 | – | VDD_LCD | 5V |
| 4, 9, 12, 15, 18, 21, 24, 27, 30 | – | GND | Ground |
| 6 | PC30 | LCD_MODULE_ENABLE | Data enable |
| 7 | PC30 | LCD_DISP | Display enable signal |
| 8 | NRTS or PC25 | NRTS or NRTS_OUT | Reset |
| 10 | PA24 | LCD_I²C_DATA | TWI Data |
| 11 | PA25 | LCD_I²C_CLK | TWI Clock |
| 13 | PA20 | MXT_IRQ | Interruption |
| 14 | PC18 | LCD_BACKLIGHT_PWM | Backlight control |
| 16 | PC13 | LCD_LVDS_D3_P | LVDS positive differential data 3 |
| 17 | PC12 | LCD_LVDS_D3_N | LVDS negative differential data 3 |
| 19 | PC7 | LCD_LVDS_D2_P | LVDS positive differential data 2 |
| 20 | PC6 | LCD_LVDS_D2_N | LVDS negative differential data 2 |
| 22 | PC11 | LCD_LVDS_CK_P | LVDS positive differential clock |
| 23 | PC10 | LCD_LVDS_CK_N | LVDS negative differential clock |
| 25 | PC5 | LCD_LVDS_D1_P | LVDS positive differential data 1 |
| 26 | PC4 | LCD_LVDS_D1_N | LVDS negative differential data 1 |
| 28 | PC3 | LCD_LVDS_D0_P | LVDS positive differential data 0 |
| 29 | PC2 | LCD_LVDS_D0_N | LVDS negative differential data 0 |
