4.2.2.3 MSS E51 Processor Watchdog Timeout Reset
(Ask a Question)The MSS can be configured such that the E51 processor’s watchdog timer causes a reset of the MSS when the timer runs out.
MSS Reset Reasons
MSS can be reset in various ways as explained in the preceding sections. The user can access the 32-bit register RESET_SR to know which reset caused the MSS to be reset. The following table lists the reasons for resetting the MSS.
| Reason | Reset Reason Bit | Asserted By | Notes |
|---|---|---|---|
| SCB_PERIPH_RESET | 0 | SCB | This is the power-on reset. This fully resets the MSS including eNVM trim values. Additional bits in the SOFT-RESET register also allow the SCB registers to be reset. |
| SCB_MSS_RESET | 1 | SCB, CPU, MSS | This resets the MSS including the Core Complex, Peripherals and all AXI infrastructure. It does not reset the eNVM trim values and SCB registers. |
| SCB_CPU_RESET | 2 | SCB, CPU, MSS | This resets the Core Complex only. This reset must not be used in most cases as the MSS requires resetting at the same time to clear outstanding AXI transactions and so on. |
| DEBUGGER_RESET | 3 | Debugger | This is asserted by the Core Complex debugger and has the same effect as the SCB_MSS_RESET. |
| FABRIC_RESET | 4 | Fabric | This signal is asserted by the fabric (MSS_RESET_N_F2M) and has the same effect as the SCB_MSS_RESET. This signal can be asserted at power-up to hold the MSS in reset. If not asserted at power-up, this signal can be used subsequently at any stage during normal operation to reset the MSS. |
| WDOG_RESET | 5 | Watchdog | This indicates that the watchdog reset has been activated. |
| GPIO_RESET | 6 | Fabric | This indicates that the fabric asserts the MSS GPIO soft reset. This resets the GPIO blocks if the GPIOs are configured to be reset by this signal. This does not reset the MSS. |
| SCB_BUS_RESET | 7 | Fabric | Indicates that SCB bus reset has occurred. |
| CPU_SOFT_RESET | 8 | CPU | Indicates that the CPU resets the MSS using the soft reset register. |
| Reserved | 31:9 | — | Reserved |
It is normal for multiple bits of RESET_SR to be enabled, as most of them are interconnected from a hardware perspective. For more information about RESET_SR, see the PolarFire SoC Register Map.