The PWM demodulator dynamically re-computes the PWM period on every
cycle.
In
most applications, the PWM period is considered to be
constant
and there is a certain temptation to simply use this well-known constant rather than
re-computing the period at the end of each cycle. The counterpoint to this notion is
that per-cycle computation of the period may be redundant, but it is also
inexpensive, costing only a subtraction of two values which must be collected for
other purposes. Also, using a compile-time, rather than a runtime period
value
for computing the duty cycle gains little in CPU usage and dynamic computation of
the period provides robustness:
The demodulator is self-configuring.
Hence,
the period need not be known ahead of time.
There are no concerns about
the precision of the constant used.
The demodulator is
self-correcting in the face of clock drift due to temperature or
voltage.
Should a device be designed
which does not use constant period, the demodulator will support it
trivially.
Indeed, there is a third option possible, wherein a calibration test is
run periodically (seconds/minutes) to re-compute the period. However, this mechanism
will inevitably affect the core timing code, and the per-cycle period computation is
so inexpensive as to compare favorably with any additional complexity from a
separate calibration mechanism.
The
following
flowcharts explain the software flow in Capture and Compare Interrupt routines:Figure 4-5. Flowchart for Timer 1
Capture ISR
Figure 4-6. Flowchart for Timer 1
Compare ISR
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