6 Device Commands and Addressing
The AT25128B/AT25256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI). The AT25128B/AT25256B utilizes an 8‑bit instruction register. The list of instructions and their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with the MSb first and start with a high‑to‑low CS transition.
| Instruction Name | Instruction Format | Operates On | Operation Description |
|---|---|---|---|
WREN | 0000 X110 | STATUS Register | Set Write Enable Latch (WEL) |
WRDI | 0000 X100 | STATUS Register | Reset Write Enable Latch (WEL) |
RDSR | 0000 X101 | STATUS Register | Read STATUS Register |
WRSR | 0000 X001 | STATUS Register | Write STATUS Register |
READ | 0000 X011 | Memory Array | Read from Memory Array |
WRITE | 0000 X010 | Memory Array | Write to Memory Array |