11.13.18 PIR0

Peripheral Interrupt Request Register 0

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
IOCIF is a read-only bit. To clear the interrupt condition, all bits in the IOCxF registers must be cleared.
The CSWIF interrupt will not wake the system from Sleep. The system will sleep until another interrupt causes the wake-up.

Name:	PIR0
Address:	0x4B3


Bit	7	6	5	4	3	2	1	0
	IOCIF	CRCIF	CLC1IF	NVMIF	CSWIF	OSFIF	HLVDIF	SWIF
Access	R	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – IOCIF Interrupt-on-Change Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 6 – CRCIF CRC Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – CLC1IF CLC1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – NVMIF NVM Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – CSWIF Clock Switch Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 2 – OSFIF Oscillator Failure Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 1 – HLVDIF High/Low-Voltage Detect Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 0 – SWIF Software Interrupt Flag

Value	Description
1	Interrupt will trigger (bit is set and cleared by user software)
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. IOCIF is a read-only bit. To clear the interrupt condition, all bits in the IOCxF registers must be cleared. The CSWIF interrupt will not wake the system from Sleep. The system will sleep until another interrupt causes the wake-up.