3.2 Crystal Oscillator
The XTO is an amplitude-regulated Pierce oscillator with internal load capacitances on the XTAL1 and XTAL2 pins of 14 ± 0.7 pF (see parameter no. 14.10 in Electrical Characteristics. The capacitance accuracy of ±0.7 pF is determined by the FETN4.CTN[3:0] register, which is copied from the factory-locked EEPROM during system initialization. Due to additional board parasitics of about 1 pF on each side, the total capacitance for CL1 and CL2 amounts to 15 ± 0.7 pF and the load capacitance specification CL for the crystal is 7.5 pF.
The crystal oscillator is enabled if the RF front-end register FEEN1.XTOEN is set to
‘1
’. The AVCC voltage must be switched on with SUPCR.AVEN set to
‘1
’ and the starting time of the AVCC supply regulator taken into
account.
After the crystal oscillator output amplitude has reached a defined level, the RF front-end
status register FESR.XRDY bit is set to ‘1
’ by the XTO. The XTO clock
is then available for the fractional-N PLL and the AVR.
The XTO oscillation frequency fXTO is the reference frequency for the fractional N PLL. When designing the system in terms of receive and transmit frequency offset, the accuracy of the crystal and the XTO must be considered as well.
The additional pulling of the XTO is lower than ±10 ppm for a motional capacitance of Cm = 4 fF including the integrated load capacitors. If the initial tolerance is compensated by the fractional-N PLL, a pulling due to temperature and supply voltage of ±4 ppm remains (see parameters no. 13.40 and 13.50 in Electrical Characteristics).
For the ATA8510/15, the pulling P amounts from -9.3 ppm to +10.1 ppm using the following values:
- Cm = 4 fF
- C0 = 1.0 pF
- CLN = 7.5 pF
- CL1,2 = 15 pF ± 0.7 pF
To ensure proper start-up behavior of the XTO, the small signal gain and the negative resistance provided by the XTO at start-up is very large. For example, the oscillation starts up even in a worst-case scenario with a crystal series resistance of 950Ω at C0 ≤ 1 pF. An approximation of the negative resistance seen by the crystal is:
Z1, Z2 are complex impedances at the XTAL1 and XTAL2 pins, therefore,
Z1 = -j/(2 x π x fXTO x CL1) + 5Ω and Z2 = -j/(2 x π x fXTO x CL2) + 5Ω
Z3 consists of C0 in parallel with an internal 180kΩ resistor, therefore, Z3 = -j/(2 x π x fXTO x C0) // 180 kΩ
gm is the internal transconductance between XTAL1 and XTAL2 with typically 40 ms at 25°C during start-up.
With fXTO = 24.305 MHz, gm = 40 ms, CL = 7.5 pF, C0 = 1 pF, a typical negative resistance of about -1,300Ω can be reached. The worst case for technological, supply voltage and temperature variations is for C0 ≤ 1 pF always better than -950Ω at Tamb = 105°C and -1,100Ω at Tamb = 85°C (see parameters no. 13.80 and 13.90 of the Electrical Characteristics).
After about 11τ, an amplitude detector detects the oscillation amplitude and sets
FESR.XRDY to ‘1
’ if the amplitude has reached a defined value.
Microchip recommends using a crystal with Cm = 4 fF to 10 fF, CLN = 8 pF, Rm < 110Ω and C0 =1.0 pF to 2 pF.
Lower values of Cm increase the start-up time and influence the system timings, whereas, higher values of Cm (up to 10 fF) increase the pulling.
Higher values of C0 reduce the negative resistance experienced by the crystal. Care must, therefore, be taken on the additional PCB capacitance between XTAL1 and XTAL2 and a crystal with low C0 must be chosen.
The ATA8510/15 crystal oscillator is a low-power design. A large start current is applied to the XTO core transistor enabling a start-up with up to 1100Ω cold-start resistance at Tamb = 85°C (see parameter no. 13.90 in Electrical Characteristics). After a successful start-up, the current is reduced and the maximum achievable series resistance, thus, reduced to 110Ω (see parameter no. 14.00 of the Electrical Characteristics).
In summary, the following front-end register settings are affected by the XTO:
- FEEN1. XTOEN: Enables/disables the XTO
- FESR.XRDY: Indicates that the XTO is ready to be used as system clock source
- FETN4.CTN4[3:0]: Calibration value for internal XTO load capacitance