3.8 RF Front-End Register Description

The registers described in this section are located in the RF front end and are accessible by an on-chip bridge interface. They are mapped to the extended I/O memory space. A read access to a front-end register generates three wait states to complete.

In standard applications, the RF front-end registers are controlled exclusively by firmware and the sequencer state machine. The registers are changed according to the application-specific settings stored in the EEPROM. Manual access to these registers by the user is not recommended.

The description in this section is intended to serve as an overview. The complete register map shows in Register Map.

The RF front-end registers are all reset to ‘0’ with RST_AVCC_N = 0. This occurs automatically when the RF front end is completely disabled by setting AVEN = 0. Reading one of the registers while the front end is disabled always returns ‘0’.