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3
Hardware
3.9
Sequencer State Machine
Features
1
General Product Description
2
System Functional Description
3
Hardware
3.1
Overview
3.2
Crystal Oscillator
3.3
Fractional-N PLL
3.4
Receive Path
3.5
Transmit Path
3.6
Data and Support FIFOs
3.7
SPDT RF Switch and Automatic Antenna Tuning
3.8
RF Front-End Register Description
3.9
Sequencer State Machine
3.9.1
Overview
3.9.2
Host State Machine
3.9.3
PLL Enable State Machine
3.9.4
PLL Lock State Machine
3.9.5
RX DSP Enable State Machine
3.9.6
RX DSP Disable State Machine
3.9.7
TX DSP Enable State Machine
3.9.8
TX DSP Disable State Machine
3.9.9
RX to TX State Machine
3.9.10
TX to RX State Machine
3.9.11
Get Telegram State Machine
3.9.12
Send Telegram State Machine
3.9.13
Shut Down State Machine
3.9.14
VCO Tuning State Machine
3.9.15
Antenna Tuning State Machine
3.9.16
Interaction with IO Registers
3.9.17
Sequencer State Machine Register Description
3.10
AVR Controller
3.11
Power Management
4
Application
5
Electrical Characteristics
6
Timing Characteristics
7
Appendix
8
Ordering Information
9
Package Information
10
Document Revision History
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3.9 Sequencer State Machine
