31.2 Fuse Bits
The device has three Fuse bytes. The following tables describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, '0', if they are programmed.
| Extended Fuse Byte | Bit No. | Description | Default Value |
|---|---|---|---|
| – | 7 | – | 0 |
| – | 6 | – | 0 |
| – | 5 | – | 0 |
| – | 4 | – | 0 |
| CFD | 3 | Disable Clock Failure Detection | 0 (programmed, CFD disable) |
| BODLEVEL2(1) | 2 | Brown-out Detector trigger level | 1 (unprogrammed) |
| BODLEVEL1(1) | 1 | Brown-out Detector trigger level | 1 (unprogrammed) |
| BODLEVEL0(1) | 0 | Brown-out Detector trigger level | 1 (unprogrammed) |
Note: 1. Please refer to Table. BODLEVEL Fuse Coding in System and Reset Characteristics for BODLEVEL Fuse decoding.
| High Fuse Byte | Bit No. | Description | Default Value |
|---|---|---|---|
| OCDEN(1) | 7 | Enable OCD | 1 (unprogrammed, OCD disabled) |
| JTAGEN | 6 | Enable JTAG | 0 (programmed, JTAG enabled) |
| SPIEN(2) | 5 | Enable Serial Program and Data Downloading | 0 (programmed, SPI prog. enabled) |
| WDTON(3) | 4 | Watchdog Timer Always On | 1 (unprogrammed) |
| EESAVE | 3 | EEPROM memory is preserved through the Chip Erase | 1 (unprogrammed), EEPROM not reserved |
| BOOTSZ1(4) | 2 | Select Boot Size | 0 (programmed) |
| BOOTSZ0(4) | 1 | Select Boot Size | 0 (programmed) |
| BOOTRST | 0 | Boot Reset vector Enabled | 1 (unprogrammed) |
Note:
- Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption.
- The SPIEN Fuse is not accessible in serial programming mode.
- Please refer to WDTCSR – Watchdog Timer Control Register for details.
- The default value of BOOTSZ[1:0] results in maximum Boot Size. See Boot size configuration table for details.
| Low Fuse Byte | Bit No. | Description | Default Value |
|---|---|---|---|
| CKDIV8(4) | 7 | Divide clock by 8 | 0 (programmed) |
| CKOUT(3) | 6 | Clock output | 1 (unprogrammed) |
| SUT1 | 5 | Select start-up time | 1 (unprogrammed)(1) |
| SUT0 | 4 | Select start-up time | 0 (programmed)(1) |
| CKSEL3 | 3 | Select Clock source | 0 (programmed)(2) |
| CKSEL2 | 2 | Select Clock source | 0 (programmed)(2) |
| CKSEL1 | 1 | Select Clock source | 1 (unprogrammed)(2) |
| CKSEL0 | 0 | Select Clock source | 0 (programmed)(2) |
Note:
- The default value of SUT[1:0] results in maximum start-up time for the default clock source. See Table. Start-up times for the internal calibrated RC Oscillator clock selection in Calibrated Internal RC Oscillator of System Clock and Clock Options chapter for details.
- The default setting of CKSEL[3:0] results in internal RC Oscillator @ 8MHz. See Table 'Internal Calibrated RC Oscillator Operating Modes' in Calibrated Internal RC Oscillator of the System Clock and Clock Options chapter for details.
- The CKOUT Fuse allows the system clock to be output on PORTB0. Please refer to Clock Output Buffer section in the System Clock and Clock Options chapter for details.
- Please refer to System Clock Prescaler section in the System Clock and Clock Options chapter for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.