16.3.5 Alternate Functions of Port E
The Port E pins with alternate functions are shown in this table:
| Port Pin | Alternate Function |
|---|---|
| PE6 | SCL1 (two-wire Serial Bus1 Clock Line) |
| PE5 | SDA1 (two-wire Serial Bus1 Data Input/Output Line)) |
| PE4 | AREF (Analog Reference Pin) |
| PE3 |
TXD2 (USART2 Transmit Pin) MOSI1 (SPI Bus1 Master Output/Slave Input) |
| PE2 |
RXD2 (USART2 Receive Pin) MISO1 (SPI Bus1 Master Input/Slave Output) |
| PE1 |
XTAL1 (Chip Clock Oscillator pin 1) |
| PE0 |
XTAL2 (Chip Clock Oscillator pin 2) |
The alternate pin configuration is as
follows:
- SCL1 – Port E, Bit 6
- SCL1: two-wire Serial Bus1 Clock Line.
- SDA1 – Port E, Bit 5
- SDA1: two-wire Serial Bus1 Data Input/Output Line.
- AREF – Port E, Bit 4
- AREF (Analog Reference Pin)
- TXD2/MOSI1– Port E, Bit 3
- TXD2: Transmit Data (Data output pin for the USART2). When the USART2 Transmitter is enabled, this pin is configured as an output regardless of the value of DDRE3.
- MOSI1: SPI Master Data output, Slave Data input for SPI1 channel. When the SPI1 is enabled as a slave, this pin is configured as an input regardless of the setting of DDRE3. When the SPI1 is enabled as a master, the data direction of this pin is controlled by DDRE3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTE3 bit.
- RXD2/MISO1 – Port E, Bit 2
- RXD2: Receive Data (Data input pin for the USART2). When the USART2 receiver is enabled this pin is configured as an input regardless of the value of DDRE2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTE2 bit.
- MISO1: Master Data input, Slave Data output pin for SPI1 channel. When the SPI1 is enabled as a master, this pin is configured as an input regardless of the setting of DDRE2. When the SPI1 is enabled as a slave, the data direction of this pin is controlled by DDRE2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTE2 bit.
- XTAL1 – Port E, Bit 1
- XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
- XTAL2 – Port E, Bit 0
- XTAL2: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
Table 16-16 relate the alternate functions of Port E to the overriding signals shown in Figure 16-5.
| Signal Name | PE6/SCL1 | PE5/SDA1 | PE4/AREF | PE3/TXD2/MOSI1 |
|---|---|---|---|---|
| PUOE | TWEN1 | TWEN1 | 0 | TXEN2+SPE1 • MSTR |
| PUOV | PORTE6 • PUD | PORTE5 • PUD | 0 | PORTE3 • PUD |
| DDOE | TWEN1 | TWEN1 | 0 | TXEN2+SPE1 • MSTR |
| PVOE | 0 | 0 | 0 | 1 |
| PVOV | TWEN1 | TWEN1 | 0 | TXEN2+SPE1 • MSTR |
| DIEOE | SCL1 OUT | SDA1 OUT | 0 | SPI1 MSTR OUTPUT |
| DIEOV | 1 | 1 | 0 | 1 |
| DI | SCL1 INPUT | SDA1 INPUT | 0 |
SPI1 SLAVE INPUT |
| AIO | - | - | - | - |
| Signal Name | PE2/RXD2/MISO1 | PE1/XTAL1 | PE0/XTAL2 |
|---|---|---|---|
| PUOE | RXEN2+SPE1 • MSTR | 0 | 0 |
| PUOV | PORTE2 • PUD | 0 | 0 |
| DDOE | RXEN2+SPE1 • MSTR | 0 | 0 |
| PVOE | 0 | 0 | 0 |
| PVOV | RXEN2+SPE1 • MSTR | 0 | 0 |
| DIEOE | SPI1 SLAVE OUTPUT | 0 | 0 |
| DIEOV | 1 | 0 | 0 |
| DI |
RXD2 SPI1 MSTR INPUT | 0 | 0 |
| AIO | - | - | - |