Operating Conditions
- 2.7V – 5.5V,
-40°C to +85°C, DC to 48 MHz
- 2.7V – 5.5V, -40°C to +125°C, DC to 48 MHz
Qualification
- AEC-Q100 Grade 1
(-40°C to 125°C)
Core
- Arm® Cortex®-M0+
CPU running at up to 48 MHz
- Single-cycle hardware multiplier
- Micro
Trace Buffer
- Memory
Protection Unit (MPU)
- Nested
Vector Interrupt Controller (NVIC)
Memories
- 512/256/128 KB
Flash
- 8/8/4 KB
independent Data Flash for non-volatile data storage
- 64/32/16 KB SRAM
System
- 12-channel Direct
Memory Access Controller (DMAC) with built-in CRC16/32
- 12-channel Event
System for Inter-peripheral Core-independent operations
- 16 external
interrupts (HW debounce) + 1 non-maskable interrupt
- Hardware Divide
and Square Root Accelerator (DIVAS)
- Position Decoder
(PDEC) working in quadrature, Hall or Counter mode
(optional)
Security and Safety
- Size-configurable
immutable boot section in Flash, allowing secure boot
- ECC support with
fault injection for Flash, Data Flash and SRAM (optional)
- CRC32 computation
on SRAM, Flash and Data Flash sections through the Device
Service Unit (DSU)
- MBIST testing of
SRAM
- Integrity Check
Module (ICM) to monitor memories based on secure hash algorithm
(SHA1, SHA224, SHA256), DMA assisted (optional)
- Clock failure
detection
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Advanced Analog and Touch
- Up to two 12-bit,
1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels
each (20 unique channels)
- Differential and single-ended input
- Automatic
offset and gain error compensation
- Oversampling and decimation in hardware to support 13,
14, 15 or 16-bit resolution
- One 10-bit, 350
ksps Digital-to-Analog Converter (DAC) with external and
internal outputs (optional)
- Up to four Analog
Comparators (AC) with Window Compare function
- Enhanced
Peripheral Touch Controller (PTC) with Driven Shield+
(optional)
- Up to 256
(16 x 16) mutual-capacitance channels
- Up to 32
self-capacitance channels with driven shield plus
capability for better noise immunity and moisture
tolerance
- Low-power, high-sensitivity, environmentally robust
capacitive touch buttons, sliders, and wheels
- Hardware
noise filtering and noise signal desynchronization for
high conducted immunity
- Supports
wake-up on touch from Standby Sleep mode
Communication Interfaces
- Up to eight
Serial Communication Interfaces (SERCOM), each configurable to
operate as:
- USART
with full-duplex and single-wire half-duplex
configuration
- I2C up to 3.4 MHz (High-Speed Mode)
- Serial
Peripheral Interface (SPI)
- LIN
Host/Client
- RS-485
- PMBus™,
SMBus™
- Up to two Controller Area Network (CAN) interfaces:
- Support for CAN 2.0A/B and CAN-FD (ISO
11898-1:2015)
- Up to two selectable pin locations to switch between
two external CAN transceivers without the need for an
external switch
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Clock Management
- Flexible clock
distribution optimized for low-power
- 48-96 MHz
Fractional Digital Phase-Locked Loop (FDPLL96M)
- 0.4-32 MHz
crystal oscillator (XOSC)
- 48 MHz internal
RC oscillator (OSC48M)
- 32.768 kHz
Crystal oscillator (XOSC32K)
- 32.768 kHz
internal RC oscillator (OSC32K)
- 32.768 kHz
internal Ultra-Low-Power RC oscillator (OSCULP32K)
- One frequency
meter (FREQM)
Power Management
- On-chip Voltage
Regulator (VREG) with configurable low-power mode in
standby
- Power-on Reset
(POR) and programmable Brown-out Detection (BOD)
- Idle and Standby
sleep modes (with logic and SRAM content retained)
- SleepWalking
peripherals
Input/Output (I/O)
- Up to 84
programmable I/O pins
- One Configurable
Custom Logic (CCL) (optional),which supports:
- Four
programmable Look Up Tables
- Combinatorial logic functions, such as AND, NAND, OR,
and NOR
- Sequential logic functions, such as Flip-Flop and
Latches
Debugger Development Support
- 2-wire Serial
Wire Debug (SWD) Port Interface for programming and
debugging
- Four hardware
breakpoints, two data watchpoints
- Micro Trace
Buffer (MTB) for instruction trace in SRAM
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Timers/Output compare/Input Capture
- Up to eight
16-bit Timer/Counters (TC), each with two waveform output
channels, configurable as:
- One
16-bit TC with two compare/capture channels, or period
register and one compare/capture channel
- One 8-bit
TC with period register and two compare/capture
channels
- One
32-bit TC with two compare/capture channels, by
combining two TCs
- Two 24-bit and
one 16-bit Timer/Counters for Control (TCC) (optional), with
extended functions:
- Up to
four compare channels with optional complementary
output
- Generation of synchronized pulse width modulation (PWM)
pattern across port pins
- Deterministic fault protection, fast decay and
configurable dead-time between complementary output
- Dithering
that increase resolution with up to 5 bit and reduce
quantization error
- Up to 8
waveform output channels
- PWM Channels
using TC peripherals:
- Up to two
PWM channels on each 16-bit TC
- PWM Channels
using TCC peripherals (optional):
- Eight PWM
channels on 24-bit TCC0
- Four PWM
channels on 24-bit TCC1
- Two PWM
channels on 16-bit TCC2
- 32-bit Real Time
Counter (RTC) with clock/calendar function
- Watchdog Timer
(WDT) with Window mode
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