6.4.4 MAC Filtering Block

The filter block determines which frames should be written to the FIFO interface and on to the SPI.

Whether a frame is passed to the SPI depends on what is enabled in the Network Configuration register, the contents of the specific address, type and Hash registers, and the frame's destination address and type field.

If the EFRHD bit of the Network Configuration register is not set, a frame will not be copied to memory if the MAC is transmitting in half duplex mode at the time a destination address is received.

Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all-'1' (0xFFFFFFFFFFFF) address is the broadcast address and a special case of multicast.

The MAC supports recognition of four specific addresses. Each specific address requires two registers, Specific Address Bottom (MAC_SABn) and Specific Address Top (MAC_SATn). The Specific Address Bottom register stores the first four bytes of the destination address and Specific Address Top contains the last two bytes. The addresses stored can be specific, group, local, or universal.

The destination address of received frames is compared against the data stored in the Specific Address registers once they have been activated. The addresses are deactivated at reset or when their corresponding Specific Address register Bottom is written. They are activated when Specific Address register Top is written. If a receive frame address matches an active address, the frame is written to the FIFO interface and on to the SPI.

Frames may be filtered using the type ID field for matching. Four type ID registers (MAC_TIDMn) exist in the register address space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match.

The contents of each type ID register (when enabled) are compared against the length/type ID of the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found.

The reset state of the type ID registers is zero, hence each is initially disabled.

The following example illustrates the use of the address and type ID match registers for a MAC destination address of 21:43:65:87:A9:CB:

The sequence in Table 6-1 shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom, as shown. For a successful match to specific address 1, the following address matching registers must be set up:

Specific Address 1 Bottom register (MAC_SAB1) = 0x87654321

Specific Address 1 Top register (MAC_SAT1) = 0x0000CBA9

For a successful match to the type ID, the following Type ID Match 1 register must be set up:

Type ID Match 1 register (MAC_TIDM1) = 0x80004321