6.4.9 Wall Clock

The wall clock is used for timestamps for inbound and outbound packets in the MAC and in the event capture unit, as well as for the time references used in the event generator. It is implemented as part of the MAC, so it can be configured and adjusted via accesses in MMS1.

The wall clock is implemented as a timer which increments each tick of the reference clock. The timer contains 94 bits where:

  • The 48 upper bits [93:46] represent seconds
  • The 30 lower bits [45:16] represent nanoseconds. This field resets to 0 at the end of each second.
  • The lowest 16 bits [15:0] of the timer count sub-nanoseconds. This field resets to 0 at the end of each nanosecond.

Event capture and event generation use all 48 seconds bits and all 30 nanoseconds bits. Packet time stamps accessed using the built-in features of the SPI protocol will use the least significant seconds bits, as shown in the Ethernet Frame Timestamping Section.

To set the wallclock,
  • Set the upper 16 bits of the wall clock seconds in the TSU Timer Seconds High (MAC_TSH) register
  • Set the lower 32 bits of the wall clock seconds in the TSU Timer Seconds Low (MAC_TSL) register.
  • Set the wall clock nanoseconds in the TSU Timer Nanoseconds (MAC_TN) register.
  • The wall clock sub-nanosecond portion is not set or read directly.

In addition to setting the clock time, it is also necessary to set the amount of time the clock increments on each tick of the reference clock. The nanosecond portion of the increment is set in the TSU Timer Increment (MAC_TI) register, while the sub-nanosecond portion is set using the TSU Timer Increment Sub-Nanoseconds (MAC_TISUBN) register. The LAN8650/1 uses a 25.0 MHz timer clock source and requires that the timer increment by 40.0 ns for each clock period. This is programmed by writing the value 0x00000028 to the TSU Timer Increment (MAC_TI) register. The sub-nanosecond register is not needed on initial configuration, but can be used when synchronizing the wall clock to an external clock source.