4.6.2.2 Bus Parity

The LAN8650/1 internally implements a bus that interconnects its major blocks. As an added measure of safety, a single bit even parity check is added that can detect single bit address and data faults in bus transfers. When enabled, a parity bit will be computed such that there is an equal number of ones on each of the address and data buses. Bus parity error detection is disabled by default and is enabled by setting the Parity Generation and Check Enable (PARGCEN) bit in the Bus Parity Control and Status (BUSPCS) register.

When a bus parity error is detected, the bus transaction is aborted (ignored) and the Bus Error (BUSER) status bit in the OPEN Alliance Status 1 (OA_STATUS1) register is set. If enabled, an interrupt will be asserted to the host controller which should then perform a hardware or software reset of the device. The block in which the bus parity error was detected may be read from the parity error status bits in the BUSPCS register as described in the table below.

Table 4-4. Bus Parity Errors
Bit Mnemonic	Bit Name	Description
MBMPER	MAC Buffer Manager Parity Error	Set when the MAC buffer manager detects a bus parity error
SPIPER	SPI Parity Error	Set when the SPI block detects a bus parity error
CSRBPER	Control/Status Register Bridge Parity Error	Set when the control/status register bridge detects a bus parity error
SRAMPER	SRAM Controller Parity Error	Set when the MAC SRAM controller detects a bus parity error

Fault Simulation

As an aid in the testing of application firmware safety mechanisms, bus data parity errors may be forced. When bus parity checking is enabled setting one of the bits in the BUSPCS register will cause the associated parity error to be triggered. See the following table for the various parity errors that can be injected.

Table 4-5. Bus Parity Error Injection
Bit Mnemonic	Bit Name	Description
CSRBDPERI	Control/Status Register Bridge Data Parity Error Injection	Control/status register bridge injects a read data parity error
SRAMDPERI	SRAM Controller Data Parity Error Injection	SRAM controller injects a read data parity error
MBMDPERI	MAC Buffer Manager Data Parity Error Injection	MAC buffer manager injects a data parity error on write access
MBMAPERI	MAC Buffer Manager Address Parity Error Injection	MAC buffer manager injects an address parity error on read/write access